Transistors used in ICs are susceptible to degradation due to frequent voltage swings. “Wear-out” tests are generally carried out on semiconductor devices to test the reliability of a device and the hot carrier-induced (HCI) degradation test is an example of such a “wear-out” test. In deep sub-micron technology, certain input/output (I/O) standards become more sensitive to HCI degradation. In some I/Os, the degradation is caused by voltage swings at the output transistors. As a consequence, the saturation drive current, i.e., the IDsat of a transistor, degrades significantly after constant operation under such condition.
The degradation would subsequently affect the performance and reliability of a device. In order to reduce the gradual degradation of the transistors, the electric field or voltage swing needs to be removed or at least reduced. One way to reduce the electric field seen across the source and drain terminals of a transistor is to stack up multiple transistors in order to divide the high voltage seen in an individual transistor among several transistors. This way, the voltage drop across any one transistor can be reduced. For example, when four transistors are stacked between a 12-volt power supply and ground, the average voltage across each transistor is only 3 volts. Because the transistors do not need to handle constant sudden voltage swings, their performance can be maintained for a much longer period of time.
Consequently the lifespan of an IC or a device can be substantially lengthened because of the reduced degradation in transistors. However, I/Os in an IC generally support different drive strengths and merely stacking up transistors just to support a particular I/O standard or drive strength is not efficient and may unnecessarily affect the performance of the I/Os.
Therefore, it is desirable to have an IC with transistors that can be configured to support a higher drive strength with a high voltage swing without significantly affecting the performance and reliability of the device. It is also desirable to have a mechanism that reduces performance degradation without sacrificing area or incurring additional cost.